1. Field of the Invention
This invention relates to a semiconductor device manufacturing system for determining the cause of failures in a semiconductor device which has become faulty after the division of a wafer into a plurality of chips, and also to a method of manufacturing semiconductor devices as well as a failure analyzing device.
2. Description of the Related Art
In recent years, the life cycle of electronic devices has been becoming shorter and shorter, and it has become imperative for developers to complete the designs of such electronic devices in a short period of time and to supply them to the market in a timely fashion. While the performance of semiconductor devices mounted in electronic equipment has been improved and the goal of obtaining a higher integration of circuits on a chip has been substantially achieved, a further reduction in the cost of such semiconductor devices is also an objective.
Semiconductor devices are usually manufactured by subjecting a semiconductor wafer to predetermined processing steps (wafer process) by means of several tens of types of manufacturing devices (hereinafter called collectively as “a manufacturing line”). In order to supply semiconductor devices stably at low cost, the number of non-defective products obtained from one sheet of wafer (hereinafter referred to as “yield”) or its rate (hereinafter referred to as “yield rate”) must be raised.
In general, the manufacturing devices are complicated in their construction and include many factors causing the yield rate to be lowered. Also, the yield rate will largely depend on how the manufacturing devices are used and the set conditions for the processing steps.
When starting mass-production of newly developed semiconductor devices or when adding a new manufacturing device to the manufacturing line, the manager of the manufacturing line analyses causes of failures and improves the manufacturing line and the processing steps in an effort to attain a desired yield rate.
Even after the desired yield rate has been attained, the manager of the manufacturing line endeavors to maintain a stable yield rate by always monitoring the manufacturing line in order to detect in advance any sign of a deteriorating yield rate.
Thus, unless the development of the processing steps necessary for the high-degree integration of circuits and the stabilization of such processing steps have been completed as quickly as possible, it is quite difficult to ship the needed semiconductor devices stably within an acceptable time period.
Therefore, for the development of the manufacturing line and the processing steps necessary for the manufacturing of semiconductor devices and the stabilization thereof, it is critical that the failures of the produced semiconductor devices are analyzed, that the causes of failures revealed as a result of such analysis are eliminated and to solve the problems of the manufacturing line and the processing steps which lead up to these problems.
However, since there are several tens of manufacturing devices and hundreds of processing steps involved in the manufacture of one semiconductor device, a big problem is how to quickly find in which manufacturing device or in which processing step the failure occurred. A method of finding the cause of failures has been known in which the detection is done based on the distribution of failures on the wafer of faulty semiconductor devices and the dependency of the failures on the position of wafer in the lot.
More specifically, the manufacturing device or the processing step by which semiconductor devices become faulty can be determined based on the distribution of chips of the faulty semiconductor devices on the wafer and the position of that wafer in the lot.
Japanese Unexamined Patent Application, First Publication, No. Hei 11-45919 (hereinafter referred to as “first related art”) discloses a method in which, when semiconductor substrates (wafers) are manufactured by means of a manufacturing line comprising a plurality of manufacturing devices and desired manufacturing processes (processing steps), such a determination is made based on an inspection step for inspecting the plurality of manufactured semiconductor substrates for the positions of the failures brought about on each semiconductor substrate by means of an inspection device, a failure distribution image data mapping step for designating coordinates of the position data of failures of each semiconductor substrate inspected in the inspection step on an image data composed of pixels arranged on the semiconductor substrate in a grid form and for mapping failure distribution image data on the image data by counting the numbers of failures of the plurality of semiconductor substrates for each of the grid-arranged pixels, and a failure analysis step for comparing the failure distribution image data formed in the failure distribution image data mapping step with a plurality of case databases, from which the cause of failures can be determined, to thereby identify the cause of the failures.
For example, when the distribution of failures on a wafer 100 corresponds to a pattern 111 shown in FIG. 23, it can be determined, by comparing the pattern with the case databases produced in the past, that the cause may exist in the step A. When the distribution of failures corresponds to a pattern 113, it can be determined that the cause may exist in the step C.
In the case of a process wherein one lot of wafers are processed by means of a plurality of manufacturing devices of the same type (manufacturing machine No. A and manufacturing machine No. B) in a single wafer processing, if the number of patterns 115 of the distribution of failures on wafers manufactured by the manufacturing machine No. B is greater than the number of patterns 114 of the distribution of failures on wafers manufactured by the manufacturing machine No. A as shown in FIG. 24, it can then be determined that the cause exists in the manufacturing machine No. B.
Although not disclosed in the document of the first related art, a case may happen where faulty semiconductor devices are concentrated in the lower area 102 of each wafer 100 in all the lots of wafers processed at the same time, as shown in FIG. 25. In such a case, it will be assumed that the cause of failures may exist in an immersion wet etching process where a resist or an oxide film was removed. The reason for this is that when a wafer is immersed in an etchant and then raised, the immersion time of the wafer is longer in the lower portion than in the higher portion, and in addition the etchant flows in the direction of the lower portion when the wafer is raised, so that a pattern or a thin film in the lower portion 102 of the wafer is more deeply etched.
Another case may occur where faulty semiconductor devices are concentrated in the peripheral area of the wafer 100. In this case, it can be determined that the cause of the failures is a plasma etching device. The reason for this is that the electric field may be uneven in the peripheral area in such a device.
When the number of semiconductor devices which have been judged to be faulty in a wafer numbered W1, is significantly high as compared to other wafers numbered W2 to W25 in the same lot, it may be assumed that the cause is a batch type processing step. For example, as shown in FIG. 26, the wafers numbered W1 to W25 are arranged in a direction perpendicular to their main surfaces in a carrier 502 and subjected to a wet etching with a processing liquid 501 in a processing vessel 500. In this case, each of the wafers numbered W1 to W25 is formed with circuits of semiconductor devices on that surface which is indicated by an arrow A. Each of the wafers numbered W2 to W25 has a little space on the side of the upper surface, so that the etchant already reacted tends to remain on the surface. In contrast, the wafer numbered W1 has a lot of fresh etchant on the upper surface as compared to the other wafers, so that the etching process progresses faster.
Japanese Unexamined Patent Application, First Publication, No. Hei 10-339943 (hereinafter referred to as “second related art”) discloses a method of manufacturing a semiconductor device comprising a step of exposure by means of projection through a mask or a reticle, in which chip coordinates are used to specify each position of chip on the exposed semiconductor wafer, determination then being made from the chip-coordinate data of faulty chips present on the exposed semiconductor wafer whether these faulty chips are caused by the mask or the reticle, so that the positions of failures in the mask or reticle can easily be detected in a short period of time.
When those semiconductor devices which are detected as faulty are cyclically located on the wafer 100 as shown in FIG. 27, it can be inferred that the mask or the reticle 101 may be the cause. It is here assumed that one reticle 101 is formed by four semiconductor device patterns (or exposure units) and that a failure exists in a specific area 101a thereof. When printing is made with this reticle 101 on a resist on the wafer by a stepper, failures will cyclically occur on the wafer corresponding to the specific position within the exposure unit as shown in FIG. 27. In FIG. 27, those chips marked with “x” are faulty chips.
As described above, a processing step causing failures can be identified based on the dependency of semiconductor devices which have been determined to be faulty because of their chip positions and the dependency of faulty wafers on their positions in the lot.
At present, in the analysis of failures with respect to a processing step, the identification of the process step which may have caused failures in semiconductor devices is performed based on an inspection of semiconductor devices in a wafer state.
After that, only those semiconductor devices which have passed the inspection by a wafer tester with respect to predetermined items are sealed in packages and assembled. Each semiconductor in this state is called an assembly. Thereafter, each assembly is further inspected by an assembly tester. In this case, since the number of inspection items is greater than that in the inspection made in the wafer state, those failures which have not been removed by the wafer tester can be detected, and at the same time those failures which have occurred in the assembling stage can also be detected and removed. Only those semiconductor devices which have passed these inspections are shipped as products.
The test of semiconductor devices in a wafer state is carried out by means of an expensive inspection device (a wafer tester). In this case, however, it is not possible to perform a high-speed test of operation in a wafer state due to the facts that the probe has parasitic capacitance and that it is not possible to provide in the time available a wafer tester possessing a speed comparable to the enhanced speed of semiconductor devices. Also, it is inefficient to perform, in a wafer state, tests about special items such as a breakdown test in which a high voltage is applied and an environmental test which is carried out at room, low and high temperatures. In addition, since a plurality of semiconductor devices are formed on the same semiconductor substrate in a wafer state, there is another problem that it is not possible to carry out a test on such items without the possibility that interference with other chips may occur.
Furthermore, a large number of semiconductor devices cannot be tested simultaneously, since control signals and data must be conveyed to input/output pads of semiconductor devices through a limited number of probes. In other words, the testing of semiconductor devices in a wafer state has a significant disadvantage since the number of semiconductor devices which can be tested simultaneously is limited, and the production efficiency is decreased when the test is performed in relation to many operational and electric characteristics. These are the various contributing factors that explain why the number of tests for semiconductor devices in a wafer state cannot be increased.
When testing chips in the wafer state one by one, in order to maintain productivity, a limited number of test items must be selected and twenty of these items must be processed within a test period of five minutes. In contrast, in the case of assemblies, 64 to 128 pieces can be mounted on a test board and a large number of such test boards can be subjected to a test in parallel, so that even when there are 400 items to be tested and a test period of two hours is needed therefor, the time period needed for the test for each semiconductor can be shortened.
The semiconductor devices which are judged to be faulty after assembly is not high in number as compared to the failures in the wafer test, but still exist to a certain degree. It is therefore necessary to decrease as quickly as possible not only the failure rate in the wafer stage but also the failure rate of the assemblies. However, once assembled in a package, the assembly no longer contains the information about its position in the wafer and consequently, the detection of faulty processing steps as in the first and the second related art cannot be made.
Thus, the semiconductor devices which have been judged to be non-defective in the wafer state and then sealed in packages and assembled may still contain a number of semiconductor devices which will be judged to be faulty in the above-described test, so that the conventional way of evaluating processing steps which may cause failures is disadvantageous in that an accurate evaluation of processing steps cannot be made.
In other words, the amount of data needed in the actual analysis, such as the data about semiconductors to be used in the evaluation of the processing step which may have caused failures, cannot be provided solely by the results of the test made in the wafer state.
In order to solve the above-described problems, Japanese Unexamined Patent Application, First Publication, No. Hei 04-288811 (hereinafter referred to as “third related art”) discloses a method of obtaining information about the wafer or the like of a semiconductor device which has become faulty in the market, in which information about a wafer and the chip positions of semiconductor devices on the wafer are inscribed in a chip surface of each semiconductor device as data in the form of a pattern specific to the chip during a stage of processing the wafer.
However, when a semiconductor device is judged to be faulty after assembling in a package in the method of the third related art, it is necessary to remove the resin sealing the package, read the information about the wafer and so on by checking the pattern data one at a time using a microscope and by so doing produce the distribution of the semiconductor devices, which have been judged to be faulty, on the wafer.
As described above, the above method of determining positions of chips on a wafer requires that resin sealing each package of all the semiconductor devices to be analyzed be removed and is thus disadvantageous in that it consumes a great deal of time.
Furthermore, in the above method of determining positions of chips on a wafer, since the analyzer has to read the pattern data on the chip one at a time with a microscope, it will take a lot of time to read the pattern data and it may be quite probable that errors occur in the reading of the pattern data.
In addition, once the resin of the package has been removed, the surface of the semiconductor device may be corroded by the resin removing solution, or a bonding wire connecting the semiconductor device to an external terminal may be disconnected, so that it will become impossible in practice to perform an electrical test of the assembly with the result that it is no longer possible to check which characteristics have become faulty.
Japanese Unexamined Patent Application, First Publication, No. Hei 11-45839 (hereinafter referred to as “fourth related art”) discloses a method in which a number of semiconductor chip areas each having predetermined circuit functions are formed in a predetermined wafer, whereafter information of position of each chip on the wafer is given to a memory element provided in a respective chip areas before the chips are separated from each other, thereby enabling the history of the manufacturing processes or the manufacturing data of each semiconductor chip to be easily associated with its characteristic data, as a result of which the yield rate of semiconductor products after the chip mounting can easily be improved as compared to the conventional method.
In the method of the fourth related art, an analysis of failures can be completed in a short period of time by knowing what manufacturing process history and what characteristic data in a wafer state the semiconductor device which has become faulty after assembly has. However, the document of the fourth related art does not contain any description suggesting procedures for the failure analysis, and this fourth related art is not arranged so that the first and the second related art is applied thereto.
Even when results of the test after assembly are associated with the position information of the wafer, it will not give enough data to allow an evaluation of the processing step which may have caused failures. More specifically, since the number of faulty assemblies is low as compared to the number of failures in the wafer stage, even when the distribution of failures is described in relation to the wafer positions, the data necessary for the analysis used in determining to which failure distribution pattern it corresponds may not be obtained, leading to a misleading failure distribution pattern.
Furthermore, in the fourth related art the position information of the wafer has to be provided in addition to the original function of the semiconductor device, as a result of which the chip size will be increased and efforts to reduce costs will be hampered.